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Reduce or Eliminate Diagnostic-based NFF’s, CND’s and RTOK’s

Diagnostic Assessment of BIT and Sensors

Design for Test (DFT) and Designing for Testability (DFT):

These are two related but separate endeavors. The Design for Test (DFT) and Design for Testability (DFT)processes and objectives are very often confused among experts in the two separate design discipline(s).

Design for Test is typically performed solely for electronic design components (chips, circuit boards, sets of circuit boards) at the lowest levels of design. As a result, Design for Test is inadvertently performed at the expense of the broader vision of the test effectiveness or value at the fielded product (Integrated Systems’ Level). Whereas Design for Testability can reuse the investment into Design for Test to validate the test coverage effectiveness at the higher and highest levels of the fielded design.

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Synchronization of On-Board BIT and Guided Troubleshooting

Ensure Sensor Corroboration and Explicit Test Coverage

With ISDD, all of the sensors used throughout the subsystems are fully described in the eXpress Diagnostic model. When the eXpress model is “processed” by eXpress, “ALL” of the interdependencies are identified and exposed to elaborate diagnostic design scrutiny, including the ability to determine the confidence or effectiveness of the sensors as used within the design architecture. As such, the Test Coverage for every sensor contained therein is fully represented and extrapolated throughout the integrated design(s), and any constraints (knowingly or unknowingly) reducing or “interfering” with the BIT Test Coverage (as may exist in any operational mode or “state”) is fully considered and reported within eXpress for better-informed design or sustainment decision-making purposes.

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Diagnostics Based on Expert Knowledge of the Diagnostic Design

Ensure Health Management Provides “Diagnostic Conclusions” to the Field

Such Health Management Implementations (IVHM, ISHM, PHM, etc.) have not typically been designed in coordination with the “bridging” of the on-board “diagnostic conclusions” to the off-board diagnostic implementation. This has been a ubiquitous shortcoming of the designing for on-board HM as it is not designed to comingle with the off-board diagnostic activities nearly as diagnostically-conclusive as it would naturally be capable of doing with ISDD.

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BIT Optimization- Validation – Integration

BIT Optimization, Validation and Integration

Traditionally, Built-in-Test (BIT) has been assigned to “test” the presence of the proper functioning at various “testing locations or points”. Such test points have often been selected by the designer or the manufacturer based upon their specific expertise or available resources. If a more careful effort was to be required, then the determining of the BIT would require additional tools, technologies, expertise and then additional resources – meaning more cost and time.

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